The present invention pertains to the technical field of data reproduction devices that reproduce data stored on a recording medium while the disk-shaped recording medium, e.g., an optical disk, such as a CD (compact disc) or a DVD (digital video disc), is rotated at constant speed.
Modulated data with a prescribed number of bits in which the original digital data have been EFM modulated are stored on disk-shaped recording media (hereafter called discs), e.g., CDs or DVDs. To demodulate and reproduce these modulated data, a motor is driven, and while the disk is rotated at constant speed, an optical pickup is moved to a read position. In the read position, the optical pickup illuminates the rotating disc, the light reflected by the disc is sensed, and analog RF (radio frequency) signals that indicate the stored contents of the disc are produced.
On discs, e.g., DVDs, data are described with a CLV (constant linear velocity) system, that is, a system that maintains a constant linear speed, and reading devices often read with a CAV (constant angular velocity) system, where the angular velocity is constant, since disc rotation is easily controlled. In such cases, the read frequency of RF signals varies according to the disc read position. The RF signals are read synchronized to reference clocks, so that when the reference clock frequency is fixed, they cannot be synchronized to the RF signals and they cannot be read correctly.
In order to read the RF signals correctly, reference clock frequency must be constantly controlled to agree with the RF signal read frequency.
Letting the time corresponding to 1 bit of data be T, with DVDs, RF signals are data that have a maximum 14T pulse width, and a period of 1488T is considered one frame. One frame contains only one pulse string that has a pulse width of 14T and it is used as the frame synchronizing signal.
To reproduce reference clocks from such RF signals, the reference clock frequency must first be matched to the RF signal read frequency. For this reason, the reference clock frequency is controlled so that a number (here 14) that indicates the frame synchronizing signal period and the same number of reference clocks are output while frame synchronizing signals are output.
PLLs are often used as circuits for matching reference clock frequency and RF signal frequency. PLLs have a frequency comparison circuit, a loop filter with the input terminal connected to the output terminal of the frequency comparison circuit, and VCO (voltage-controlled oscillator) with the input terminal connected to the output terminal of the loop filter. They are constituted so that VCO output signals and RF signals will be input to the frequency comparison circuit. The frequency comparison circuit controls the VCO control voltage with RF signals as reference signals so that VCO output signal frequency and RF signal frequency will agree.
An example of a frequency comparison circuit that is used when reference clocks are produced from the RF signals of a DVD is indicated by reference number (101) in FIG. 7.
This frequency comparison circuit (101) has edge detection circuit (102), counter (103), comparator (104), maximum latch circuit (105), minimum latch circuit (106), and timing generation circuit (107).
RF signals and reference clocks for when RF signals are read are input to edge detection circuit (102), the rising/falling edge of the RF signals is detected synchronized to the reference clock that is currently being output, and detection pulses are output to counter (103).
RF signal rising/falling edge detection pulses and reference clocks are input to counter (103) and the number of reference clock pulses are counted in binary values during the period from when the edge detection pulse is input until the next edge detection pulse is input. The count value is output to comparator (104).
Comparator (104) compares the output value of counter (103) with a number (here 14) that indicates the frame synchronizing signal period and outputs the result to maximum latch circuit (105). When the output value of counter (103) is larger than the reference value xe2x80x9clargexe2x80x9d is output, when it is smaller, xe2x80x9csmallxe2x80x9d is output, and when it is equal to the reference value, xe2x80x9cequalxe2x80x9d is output to maximum latch circuit (105).
Maximum latch circuit (105) compares the current value in the latch with the output of comparator (104), and the current value is replaced with a larger value. The priority for rewriting is xe2x80x9clarge,xe2x80x9d xe2x80x9cagree,xe2x80x9d and xe2x80x9csmall.xe2x80x9d When xe2x80x9csmallxe2x80x9d is held and xe2x80x9cequalxe2x80x9d is input, it is replaced by xe2x80x9cagree,xe2x80x9d and when xe2x80x9cequalxe2x80x9d is held and xe2x80x9clargexe2x80x9d is input, it is replaced by xe2x80x9clarge.xe2x80x9d And when xe2x80x9cequalxe2x80x9d is held and xe2x80x9csmallxe2x80x9d is input, xe2x80x9cequalxe2x80x9d is held, and when xe2x80x9clargexe2x80x9d is held and xe2x80x9cequalxe2x80x9d or xe2x80x9csmallxe2x80x9d is input, xe2x80x9clargexe2x80x9d is held.
With the aforementioned circuit, each time that an RF signal edge detection pulse is output sequentially by edge detection circuit (102), the number of reference clock pulses is counted by counter (103). This number of pulses corresponds to the RF signal pulse width. With comparator (104), each time that a count value is output from counter (103), the count value and a number that indicates the frame synchronizing signal period are compared and the comparison result is output to maximum latch circuit (105).
The value held in maximum latch circuit (105) is reloaded each time that a comparison result is input. This held value is reset by timing generation circuit (107) at time intervals that include at least one frame. Immediately before it is reset, the value held by maximum latch circuit (105) will be equal to the result of comparing the maximum value of the pulse width actually detected during one frame and a number that indicates the frame synchronizing signal period. The held value obtained in this way is output to minimum latch circuit (106).
Minimum latch circuit (106) compares the current value held in the latch with the output value of maximum latch circuit (105), and the current value is replaced with a smaller value. The priority for rewriting is xe2x80x9csmall,xe2x80x9d xe2x80x9cagree,xe2x80x9d and xe2x80x9clarge.xe2x80x9d When xe2x80x9clargexe2x80x9d is held and xe2x80x9cequalxe2x80x9d is input, xe2x80x9cequalxe2x80x9d is held, and when xe2x80x9cequalxe2x80x9d is held and xe2x80x9csmallxe2x80x9d is input, xe2x80x9csmallxe2x80x9d is held. When xe2x80x9cequalxe2x80x9d is held, if xe2x80x9clargexe2x80x9d is input, xe2x80x9cequalxe2x80x9d is held, and when xe2x80x9csmallxe2x80x9d is held, if xe2x80x9cequalxe2x80x9d or xe2x80x9clargexe2x80x9dis input, xe2x80x9csmallxe2x80x9d is held.
The value held by minimum latch circuit (106) is reset at time intervals that include multiple frames by timing generation circuit (107). During the period before reset, the results of comparing the maximum value of the pulse width actually detected in one frame and a number that indicates the frame synchronizing signal period are input multiple times from maximum latch circuit (105). Minimum latch circuit (106) holds the comparison result that corresponds to the smallest of those values.
As described above, one of the values xe2x80x9clarge, xe2x80x9cagree,xe2x80x9d or xe2x80x9csmall,xe2x80x9d corresponding to the result of comparing the maximum value of the pulse width detected during one frame and a number that indicates the frame synchronizing signal period, is held by minimum latch circuit (106) and is output to a VCO; not shown, via a loop filter.
The VCO controls the reference clock frequency in response to the output value from minimum latch circuit (106). If the output value from minimum latch circuit (106) is xe2x80x9csmall,xe2x80x9d the reference clock frequency is lower than the RF signal read frequency. Thus, the reference clock frequency is raised by a prescribed amount. On the other hand, if the output from minimum latch circuit (106) is xe2x80x9clarge,xe2x80x9d the reference clock frequency is higher than the RF signal read frequency. Thus, the reference clock frequency is lowered to 7 a prescribed amount. By controlling the reference clock frequency in this way, the maximum value of the pulse width detected in one frame and a number that indicates the frame synchronizing signal period will agree.
The output value from minimum latch circuit (106) will be xe2x80x9cequalxe2x80x9d because of this control. If the maximum value for pulse width detected in one frame and a number that indicates the frame synchronizing signal period are equal, the reference clock frequency will be equal to RF signal frequency. In this way, the reference clock frequency and the RF signal read frequency are matched.
After the RF signal read frequency and the reference clock frequency are matched in this way, if the reference clock phase is equal to the RF signal phase, reference clocks that correspond to RF signals can be generated. By reading RF signals synchronized to this reference clock, correct data reproduction will be possible.
However, in frequency comparison circuit (101) with the aforementioned constitution, a comparator (103) with a slow processing speed is used. The count value and the reference value must be compared each time a count value is output from counter (102), so that it has been difficult to further increase operating speed of the comparator (103).
The present invention was conceived to solve the aforementioned difficulties of the prior art. A general object of the present invention is to provide a frequency comparison circuit that will permit frequency comparison to be performed rapidly.
This and other objects, features and advantages are attained in accordance with one aspect of the invention by a frequency comparison circuit having an edge detection circuit into which serial signals that are binary data and clock signals are input and that outputs pulse signals that indicate changes in the aforementioned serial signal data, an edge spacing detection circuit into which the aforementioned pulse signals and the aforementioned clock signals are input and that outputs numerical data that indicate the aforementioned clock signal frequency corresponding to the period during which there are no changes in the aforementioned serial signal data, and a maximum value memory circuit into which the aforementioned numerical data, the aforementioned clock signals, and a first reset signal are input, that stores the maximum value of the aforementioned numerical data in response to the aforementioned clock signals and that also resets the stored maximum value in response to the aforementioned first reset signal.
Another aspect of the invention comprises a frequency comparison circuit with a value minimum memory circuit into which the aforementioned maximum value, the aforementioned first reset signal, and a second reset signal are input, which stores and outputs the minimum value of the aforementioned maximum value in response to the aforementioned first reset signal and also resets the aforementioned minimum signal in response to the aforementioned second reset signal.
A further aspect of the invention includes a frequency comparison circuit having an edge spacing detection circuit that includes a series transistor. The aforementioned numerical data are formed by sequentially shifting a first value or second value from the initial level of the aforementioned series transistor in response to the aforementioned clock signals when the aforementioned pulse signals are a first value or a second value and the aforementioned series transistor is reset by logic changes in the aforementioned pulse signals.
A fourth aspect of the invention includes a frequency comparison circuit having a maximum spacing detection circuit that includes multiple first unit memory circuits that correspond to the prescribed level of the aforementioned series transistor. And each of the aforementioned unit memory circuits finds the aforementioned maximum value by calculating the logical sum of prescribed bits of the aforementioned numerical data and a stored value.
A fifth aspect of the invention comprises frequency comparison circuit described in claim 4, where the aforementioned minimum value detection circuit includes multiple second unit memory circuits that correspond to the aforementioned multiple first unit memory circuits. And each of the aforementioned second unit memory circuits finds the aforementioned minimum value by calculating the logical sum of prescribed bits of the aforementioned maximum value and a stored value.
A sixth aspect of the invention includes a frequency comparison circuit having an output circuit that finds frequency comparison signals from differences in values of adjacent aforementioned first unit memory circuits and aforementioned second unit memory circuits.
With the frequency comparison circuit of the present invention, the edge spacing detection circuit can detect the number of clock signal pulses by storing a first value continuously from the top of the serial register that is equal to the number of clock signal (reference clock) pulses input.
A maximum value detection circuit is finished for the aforementioned comparison circuit. When the number of multiple clock signal pulses is detected, multiple first unit memory circuits that correspond to prescribed stages of the aforementioned serial registers detect the maximum value of the number of clock pulse signals by calculating the logical sum of prescribed bits of the numerical data output from the aforementioned serial register and a stored value.
With the constitution described above, once a first value is stored in each of the first unit memory circuits of the maximum value detection circuit, even if the prescribed bits of the aforementioned numerical data change to a second value, the first value will continue to be stored. Thus, with each of the first unit memory circuits of the aforementioned maximum value detection circuit, the number of first unit memory circuits in which the first value is stored may increase, rather than decrease.
By letting the number of first unit memory circuits in which the first value is stored correspond to the number of clock signal pulses during the period when there are no logic level changes, the first value will be stored in each of the first unit memory circuits of the maximum value detection circuit in a the number corresponding to the maximum value of clock signal pulses that are detected multiple times.
In a frequency comparison circuit with this constitution, when serial signals are used as RF signals, a first value is stored in the maximum value detection circuit in a the number that corresponds to the frame synchronizing signals that has the maximum pulse width of the RF signals and the number of clock pulse signals can be detected according to the maximum pulse width of the RF signals. Thus, the magnitude of the RF signal read frequency and the clock signal frequency can be compared.
In the past, to compare the RF signal read frequency and the clock signal frequency, a low-speed counter or comparator or the like would have been used, but the frequency comparison circuit of the present invention can be constituted with string of registers, e.g., shift registers (serial registers). It is not necessary to use counters or comparators, and operating speed can be improved compared to the past.
Note that the frequency comparison circuit of the present invention could also be constituted to reset the contents stored in each of the first unit memory circuits in the maximum value detection circuit to a second value with a first reset signal. Particularly when the RF signal read frequency and the clock signal are compared, the number of clock signal pulses can be found by resetting each frame and when the maximum pulse length in one frame, which is the frame synchronizing signal, is output.
Also, an output circuit that outputs frequency comparison signals could also be furnished in the frequency comparison circuit of the present invention. It is possible to detect positions where the stored contents are different according to this output circuit. The positions where stored contents are different correspond to the number of clock signal pulses, so that errors between the clock signal frequency and the RF signal read frequency can be found.
In addition, the frequency comparison circuit of the present invention could also be constituted with a minimum value detection circuit.
By constituting it in this way, once a second value is stored in each of the second unit memory circuits in the minimum value detection circuit, even if the prescribed bits of the aforementioned numerical data then become the first value, the second value will continue to be stored. Thus, with each of the second unit memory storage circuits in the minimum value detection circuit, the number of second unit memory circuits in which the second value is stored may increase, rather than decrease. On the other hand, the number of second unit memory circuits in which the first value is stored may decrease, rather than increase.
The number of first unit memory circuits in which the first value is stored corresponds to the number of clock signal pulses, as stated above. So that the first value will be stored in a number that corresponds to the smallest value of the maximum values of the number of clock signal pulses detected multiple times, in each of the second unit memory circuits in the minimum value detection circuit.
Especially when the serial signals are RF signals, a non-signal state may occur due to an abnormality, a value larger than the maximum value of the original number of clock signal pulses may be detected, and a malfunction may therefore occur. But with the aforementioned minimum value detection circuit, multiple maximum values are sampled and the smallest of these values is used as the maximum value; in this way, a non-signal state will not be detected as a maximum value. Thus, it is possible to be sure that a malfunction will not occur due to the detection of a non-signal state as a maximum value.
Note that the frequency comparison circuit of the present invention could also be constituted so that the stored contents of each of the second unit memory circuits in the minimum value detection circuit could be reset to a second value with a second reset signal.